In the fabrication of semiconductor devices, numerous conductive device regions and layers are formed in or on a semiconductor substrate. To isolate underlying regions or layers, an inter layer dielectric is formed over those regions. In most modern processes chemical vapor deposition is performed, wherein a solid film of oxide is formed on a substrate by the reaction of an oxide source gas and the substrate. Various parameters such as the oxide source and deposition method influence the characteristics of the resulting inter layer dielectric. In chemical vapor deposition the gas mixture, temperature, RF power, pressure, and gas flow rate, among other factors, may be varied to achieve the desired characteristics.
In many current applications, the inter layer dielectric (ILD) has to conform to exacting specifications. There should be no voids between metal lines at any layer that is above the metal surface in void height, or greater than 25% of the metal spacing in void width. Voids larger than that can be uncovered during further processing causing problems. Composite ILD stress at the post polish thickness should be between 1.0e08 to 9.0e08 dyne/square-cm, compressive. If the inter layer dielectric is not compressive enough, it will result in cracking and short circuits. If the ILD layer is too compressive, it can result in poor oxide metal adhesion which can lead to open circuits within the device. These specifications can not be achieved with present processes.
Smaller semiconductor transistors are formed by decreasing the channel length of the transistor. A problem with manufacturing such small channel devices is that the aspect ratios of various structures on these transistors increases. Aspect ratio is the proportion of the height of a structure to its width. In general, aspect ratio refers to the dimensions of the spaces between structures. Thus, for example, metal aspect ratio describes the ratio of the metal height to the space between the metal structures.
As device sizes shrink, the distance between metal structures on the wafer decreases. Resistance, however, is inversely related to cross sectional area in metals. Increased resistance has numerous disadvantages including increased power consumption and heat emission. Thus, scaling down metal cross sections is disadvantageous. One solution to this is to increase the height of the metal. This, however, leads to increased metal aspect ratios.
Presently, there are a number of methods to deposit inter layer dielectrics. One currently used method is shown in FIGS. 1A-E. Substrate 100 represents a semiconductor substrate and any device layers or structures underlying the metal structures 110 thereon. In order to isolate these metal structures 110 from subsequent layers, a first layer of dielectric 130 is deposited using a plasma enhanced chemical vapor deposition method. Tetraethylorthosilicate (TEOS) is used as the oxide source in this deposition. The first layer of dielectric 130 is relatively conformal and high in quality. The deposition profile of the first layer 130 is tapered by an argon sputter etch 140. The argon sputter etch removes oxide from the upper edges, and redeposits part of that oxide in the corners formed by the metal structures 110 and the substrate 100. This redeposited oxide 145 helps taper the deposition profile. A second layer 150 of oxide is then deposited, also using a plasma enhanced chemical vapor deposition method with TEOS as the oxide source (PTEOS). This second layer 150 is a thick sacrificial layer. This second layer 150 then planarized 160.
Although this method was useful in the past, it does not meet the ILD criteria set out above. When aspect ratios increase to 1.5:1 or greater, ILD produced by this process will have voids that exceed 25% of metal width and are higher than the metal surface in height. Thus, this method can not be extended to transistors incorporating aspect ratios of 1.5:1 of greater.
An alternative prior art process is shown in FIGS. 2A-F. A first layer of oxide 230 is deposited over the metal structures 210 on the substrate 200. The first layer is deposited using plasma enhanced chemical vapor deposition of TEOS material (PTEOS). The PTEOS deposited layer 230 is high in quality, compressive and relatively conformal. A nitrogen plasma treatment 240 is applied to the first layer 230. This nitrogen plasma treatment 240 creates a uniform and accepting surface for subsequent layers. A second layer 260 is then deposited using a sub atmospheric chemical vapor deposition (SACVD) of TEOS material. The SACVD produces a lower quality dielectric 260, which is tensile. This layer 260 is then followed by a sacrificial layer 270 formed with the PTEOS method. The sacrificial layer 270 is then planarized 280.
This process can be used for gapfill at 1.0 to 1.5:1 aspect ratios. However, in order to achieve the void specifications described above, the thickness of the SACVD layer 260 used must be greater than 60% of the metal height. Since the SACVD layer 260 is highly tensile, compressive PTEOS layers 230, 270 are needed to balance the SACVD layer 260. Therefore, the ILD resulting from this method is thick. This not only increases overall device size, it also causes problems when vias are formed through the ILD. As the ILD increases in thickness, the aspect ratio of the via increases as well. This causes problems in forming and filling the vias. Therefore, this method is not workable for metal aspect ratios of 1.5:1 or greater.
Thus it is desirable to find a method of depositing an ILD layer that allows for aspect ratios of 1.5:1 or greater, and retains a compressive quality, while not requiring excessive ILD height.